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- Re: Intel and AMD RDMA implementation
In article <87y6csnfdz....@Pulska.kon.iki .fi>,
That is certainly possible, and I wondered about that possibility.
If it IS the intention, then POSIX contains no constraints on even
writing to a buffer while data are being read into it asynchronously.
Anyone With Clue will know that is undefined behaviour, but .... - Re: Intel and AMD RDMA implementation
To me, changing "the process memory space" suggests mmap-like
operations that change the space itself rather than just write to
the memory in it. In which case, the outstanding asynchronous
I/O might keep using the original mapping or not. Although the
spec also says the behavior is undefined if the related address - Re: Effects of Memory Latency and Bandwidth on Supercomputer,Application Performance
No, not at all.
To me, the most interesting part of that paper was the way they had to
tune their 2D decomposition for the actual core layout, i.e. with 16
cores/node the most efficient setup was with 4xN "pencils", almost
certainly due to those 16 cores coming from 4 4-core CPUs.
The other highly significant piece of information was that they got away - 100% free dell laptaps offerd by dell and Vodafone companies.
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my blog is [link] - Re: Effects of Memory Latency and Bandwidth on Supercomputer,Application
But is there anyone who does it for routing? And why did cut-through
pretty much disappear for gigabit switching, only to reappear for 10
Gbps? Except for HP who seem to be stuck with store-and-forward, but
maybe that is why they bought 3com.
/Benny - Re: Effects of Memory Latency and Bandwidth on Supercomputer,Application Performance
In article <5fb1774d-6056-4564-a6c8-4c991 9a50...@j8g2000yqd.googlegroup s.com>,
Are [link] and
[link] relevant in
this case? Large 3D FFTs decomposing over lots of processors into
(N/x)*(N/y)*N bricks, just over 100 seconds for 8192^3 on 2^15 CPUs - Re: Effects of Memory Latency and Bandwidth on Supercomputer,Application
In article <rcl8i7-aco....@ntp.tmsw.no>,
And bring down latency. A lot, actually. Naive store and forward of a
12400 bit (farming included) frame on a gigabit link uses around 86 us.
Add some store/handling logic, and you are close to 100.
Modern gigabit switches bring this latency down to below 10. and, yes, there - Re: Redbook on the new z196 mainframes.
The best answer I've received is that it's the best model for the target
application anyone could construct without giving away details.[1]
I'll try to remember to come back and answer more clearly after a
funding agency makes its announcement, but there will be a higher-level
benchmark within a dev. program that focuses on graphs involving random - I HACK $2000 FROM PAYPAL
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and enter your PayPal id And Your name. - Re: Intel and AMD RDMA implementation
In article <f2mai7-jes....@ntp.tmsw.no>,
Yes, er, unobviously :-)
No, I meant what I said, but meant 'being written to the device'.
I strongly disagree, in a well-designed asynchronous interface, but
I strongly agree in a POSIX-like one!
Regards,
Nick Maclaren. - Re: Intel and AMD RDMA implementation
That is so obvious that it shouldn't even need to be written down.
Unfortunately "obvious" is obviously a very non-obvious term, or
something like that.
So you meant to write 'in the process of being read'?
Right. Like, if the OS knows that it has exclusive access to a buffer,
it can employ all sorts of dirty tricks with safety, up to and including - Re: Intel and AMD RDMA implementation
In article <f50456ph3g65flpulq3n1bin6pdli l7...@4ax.com>,
Eh? I was quoting the specification itself!
In all reasonable standards, explicit constraints supersede implicit
ones. And the explicit constraint on when and how a buffer may be
used is what I quoted.
That's irrelevant. What is at issue is what an implementation is - Re: Intel and AMD RDMA implementation
In article <e01ddfe6-280f-485d-87ae-5b8b9 c6f0...@l20g2000yqm.googlegrou ps.com>,
The case of reading a buffer that is in the process of being written
(i.e. two read-only actions) is debatable. I agree with you, but
there are arguments in the other direction.
Regards,
Nick Maclaren. - Re: Redbook on the new z196 mainframes.
Itanium's 128 byte cache line seems positively puny then :)
rick jones - Re: Intel and AMD RDMA implementation
Well, you know, some of us were proposing asynchronous I/O at the same
time as threading. (I wasn't on POSIX, but my boss was. Hi Johm if you
are out there!)
Unfortunately, I think it was HP that came along with an asynch proposal
that they had implemented on top of kernel threading. Which ruined their